// Copyright (C) 1953-2023 NUDT
// Verilog module name - frame_injection_control   
// Version: V4.3.0.20230309
// Created:
//         by - fenglin 
////////////////////////////////////////////////////////////////////////////
// Description:
//         receive and process pkt from host.
//             - top module.
///////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ps

module frame_injection_control
#(
parameter clk_period = 24'h080000//8ns
)
(
        i_clk                            ,
        i_rst_n                          ,
                                         
        iv_addr                          ,      
        iv_wdata                         ,           
        i_wr_sis                         ,
        i_rd_sis                         , 
        i_wr_sim                         ,
        i_rd_sim                         ,         
                        
        o_wr_sis                         ,
        ov_addr_sis                      ,
        ov_rdata_sis                     ,
        o_wr_sim                         ,
        ov_addr_sim                      ,
        ov_rdata_sim                     , 

        i_st_rxenable                    ,
        i_cycle_start                    ,
        iv_time_slot_length              ,
        iv_time_slot_period              ,

        i_desp_wr_hcp                    ,
        iv_desp_hcp                      ,
               
        i_desp_wr_host                   ,
        iv_desp_host                     ,
        //iv_st_inject_dbufid_host         ,      
        
        ov_desp_network                  ,
        o_desp_wr_network                ,
		
		ov_desp_host                     ,
		o_desp_wr_host                   ,
		i_desp_ack_host                  ,
        
        ov_st_stream_state               ,
        i_st_inject_overflow_pulse        
);
// I/O
// clk & rst
input                  i_clk                     ;
input                  i_rst_n                   ; 

input       [18:0]     iv_addr                   ;
input       [31:0]     iv_wdata                  ;
input                  i_wr_sis                  ;
input                  i_rd_sis                  ;
input                  i_wr_sim                  ;
input                  i_rd_sim                  ;

output                 o_wr_sis                  ;
output      [18:0]     ov_addr_sis               ;
output      [31:0]     ov_rdata_sis              ;
output                 o_wr_sim                  ;
output      [18:0]     ov_addr_sim               ;
output      [31:0]     ov_rdata_sim              ; 

input                  i_st_rxenable             ;
input                  i_cycle_start             ;
input       [10:0]     iv_time_slot_length       ;
input       [10:0]     iv_time_slot_period       ;            
//desp receive    
input       [35:0]     iv_desp_hcp                   ;
input                  i_desp_wr_hcp                 ;

input       [16:0]     iv_desp_host                   ;
//input       [4:0]      iv_st_inject_dbufid_host       ;
input                  i_desp_wr_host                 ;

output      [11:0]     ov_desp_network                        ;
output                 o_desp_wr_network                      ;

output      [11:0]     ov_desp_host                   ;
output                 o_desp_wr_host                 ;
input                  i_desp_ack_host                ;

output      [31:0]     ov_st_stream_state         ;
input                  i_st_inject_overflow_pulse ;
/////////////////////////////////////////////////////////// 
wire                   w_rcbe_desp_wr_ddi2dmu  ;
wire        [11:0]     wv_rcbe_desp_ddi2dmu    ;
wire                   w_rcbe_desp_ack_dmu2ddi ;

wire                   w_ts_injection_addr_ack;
wire        [4:0]      wv_ts_injection_addr   ; 
wire                   w_ts_injection_addr_wr ; 

wire                   w_st_desp_wr_ddi2sim       ;
wire        [11:0]     wv_st_desp_ddi2sim         ;
wire        [4:0]      wv_st_inject_dbufid_ddi2sim;

wire        [11:0]     wv_st_desp_sim2dmu         ;  
wire                   w_st_desp_wr_sim2dmu       ;
wire                   w_st_desp_ack_dmu2sim      ;

wire        [11:0]     wv_desp_dea2dmu            ; 
wire                   w_desp_wr_dea2dmu          ;
wire                   w_desp_ack_dmu2dea         ;

descriptor_dispatch descriptor_dispatch_inst 
(
        .i_clk              (i_clk                      ),
        .i_rst_n            (i_rst_n                    ),
                                                        
        .iv_desp            (iv_desp_host[11:0]         ),       
        .iv_st_inject_dbufid(iv_desp_host[16:12]        ),
        .i_desp_wr          (i_desp_wr_host             ),
        
        .o_st_desp_wr       (w_st_desp_wr_ddi2sim       ),           
        .ov_st_desp         (wv_st_desp_ddi2sim         ),         
        .ov_st_inject_dbufid(wv_st_inject_dbufid_ddi2sim),  
        
        .o_rcbe_desp_wr     (w_rcbe_desp_wr_ddi2dmu     ),
        .ov_rcbe_desp       (wv_rcbe_desp_ddi2dmu       ),
        .i_rcbe_desp_ack    (w_rcbe_desp_ack_dmu2ddi    )
); 

descriptor_ack HCP_descriptor_ack_inst
(
       .i_clk                 (i_clk     ),
       .i_rst_n               (i_rst_n   ),
                                         
       .iv_desp               (iv_desp_hcp   ),
       .i_desp_wr             (i_desp_wr_hcp ),
                                         
       .ov_desp_network       (wv_desp_dea2dmu   ),
       .o_desp_wr_network     (w_desp_wr_dea2dmu ),
       .i_desp_ack_network    (w_desp_ack_dmu2dea),
	   
        .ov_desp_host         (ov_desp_host   )         ,
        .o_desp_wr_host       (o_desp_wr_host )         ,
        .i_desp_ack_host	  (i_desp_ack_host) 
);
    
st_injection_schedule 
#(
.clk_period(clk_period)
)
st_injection_schedule_inst(
.i_clk                          (i_clk                      )  ,
.i_rst_n                        (i_rst_n                    )  ,

.iv_addr                        (iv_addr                    )  ,
.iv_wdata                       (iv_wdata                   )  ,
.i_wr                           (i_wr_sis                   )  ,
.i_rd                           (i_rd_sis                   )  ,                                                             
.o_wr                           (o_wr_sis                   )  ,
.ov_addr                        (ov_addr_sis                )  ,
.ov_rdata                       (ov_rdata_sis               )  ,

.i_st_rxenable                  (i_st_rxenable              )  ,   
.i_cycle_start                  (i_cycle_start              )  ,
.iv_time_slot_length            (iv_time_slot_length        )  ,
                                                               
.i_ts_injection_addr_ack        (w_ts_injection_addr_ack    )  ,
.ov_ts_injection_addr           (wv_ts_injection_addr       )  ,
.o_ts_injection_addr_wr         (w_ts_injection_addr_wr     )  ,
                                                               
.iv_injection_slot_table_period (iv_time_slot_period        )  ,
.ism_state                      (                           )  
);

st_injection_management st_injection_management_inst(
.i_clk                   (i_clk                        )  ,
.i_rst_n                 (i_rst_n                      )  ,
                                                       
.iv_addr                 (iv_addr                      )  ,
.iv_wdata                (iv_wdata                     )  ,
.i_wr                    (i_wr_sim                     )  ,
.i_rd                    (i_rd_sim                     )  ,                                                             
.o_wr                    (o_wr_sim                     )  ,
.ov_addr                 (ov_addr_sim                  )  ,
.ov_rdata                (ov_rdata_sim                 )  ,
                        
.iv_ts_descriptor        (wv_st_desp_ddi2sim           )  ,
.i_ts_descriptor_wr      (w_st_desp_wr_ddi2sim         )  ,
.iv_ts_descriptor_waddr  (wv_st_inject_dbufid_ddi2sim  )  ,
                                                          
.iv_ts_injection_addr    (wv_ts_injection_addr         )  ,
.i_ts_injection_addr_wr  (w_ts_injection_addr_wr       )  ,
.o_ts_injection_addr_ack (w_ts_injection_addr_ack      )  ,
                         
.ov_ts_descriptor        (wv_st_desp_sim2dmu           )  ,
.o_ts_descriptor_wr      (w_st_desp_wr_sim2dmu         )  ,
.i_ts_descriptor_ack     (w_st_desp_ack_dmu2sim        )  ,

.ov_st_stream_state      (ov_st_stream_state           )
);      

descriptor_select descriptor_select_fic(
.i_clk                   (i_clk                    ),
.i_rst_n                 (i_rst_n                  ),

.iv_desp_1               (wv_st_desp_sim2dmu       ),
.i_desp_wr_1             (w_st_desp_wr_sim2dmu     ),
.o_desp_ack_1            (w_st_desp_ack_dmu2sim    ),

.iv_desp_2               (wv_rcbe_desp_ddi2dmu     ),
.i_desp_wr_2             (w_rcbe_desp_wr_ddi2dmu   ),
.o_desp_ack_2            (w_rcbe_desp_ack_dmu2ddi  ),
                         
.iv_desp_3               (wv_desp_dea2dmu   ),
.i_desp_wr_3             (w_desp_wr_dea2dmu ),
.o_desp_ack_3            (w_desp_ack_dmu2dea),

.ov_bufid                (ov_desp_network[8:0]             ),
.ov_ipv                  (ov_desp_network[11:9]            ),
.o_bufid_wr              (o_desp_wr_network                )
);
    
endmodule